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1 active clamp forward pwm controller ISL6726 the ISL6726 is a highly featured single-ended pwm controller intended for applications using the active clamp forward converter topology in either n- or p-channel active clamp configurations, the asymmetric half-bridge topology, and the standard forward topologies with synchronous rectification. it is a current-mode pwm controller with many features designed to simplify its use. among its many features are a precision oscillator which allows accurate control of the deadtime and maximum duty cycle, bi-directional synchronization with 180 phase shift for interleaving applic ations, adjustable soft-start and soft-stop, a low power disable mode, and average current limit for ?brick-wall? overcurrent protection. this advanced bicmos design features low start-up and operating currents, adjustable switching frequency to greater than 1mhz, high current fet driv ers, and very low propagation delays for a fast response to overcurrent faults. applications ? telecom and datacom power supplies ? ac/dc power supplies ? battery chargers features ? precision maximum duty cy cle and deadtime control ? 125a typical start-up current ? adjustable peak and average current limit protection ? programmable oscillator frequency ? bi-directional synchronization with 180 phase shift for interleaved converter applications ? adjustable soft-start and selectable soft-stop ? selectable minimum duty cycle clamp for synchronous rectifier applications ? programmable slope compensation ? supports n- and p-channel active clamp fets ? programmable switch timing between main and active clamp outputs ? programmable undervoltage lock-out (uv) ? input voltage dependent duty cycle clamp ? enable input with low power disable ? internal over-temperature protection ? pb-free (rohs compliant) +vin outac outm level shift -vin n- or p- channel active clamp forward asymmetric half-bridge +vin -vin outac outm outac level shift january 31, 2011 fn7654.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL6726 2 fn7654.0 january 31, 2011 pin configuration ISL6726 (20 ld qsop) top view 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 sync dclim uv enable rtc ct verr iset fb cs delay vref gnd mode outm vdd outac slope iout ss pin descriptions pin # symbol description 1 sync a bi-directional edge-sensitive signal used to synchronize multiple devices together. if the sync pins of two units are co nnected, they will synchronize 180 degrees out of phase with each other. this feature facilitates th e design of interleaved topologies. if mo re than two units are connected, one will be the master unit and the re st will be slave units. all of the slave units will synchronize 180 degrees out-of-phase with the master. the master designation is not fixe d or predetermined and is self-arbitrating. the master is deter mined by the fastest running oscillator on a dy namic basis. sync may also be used to synchronize to an external clock. 2 dclim used in conjunction with uv, dclim creates a duty cycle cl amp that is dependent on the in put voltage. as the input voltag e increases, the maximum allowed duty cycle decreases. this feature is necessary in the active clamp forward to help prevent transformer cor e saturation during transients. a resistor divi der from vref sets the threshold of dclim. 3 uv sets the user programmable undervoltage threshold. placing a resistor divider from the input voltage to ground and set to 1. 00v determines the minimum operating voltage. the amount of hysteresis is determined by an internal current source and set by the external impedance of the divider. the curren t source is active when uv is below 1v. 4 enable a logic level signal used to enable the ic. when the input is open, the ic is enabled and a soft-start cycle begins if n o fault conditions are present. when pulled low, the outputs are disabled and the ic enters a low power sleep state. if soft-stop is enabled, a lo gic ?0? on enable forces a soft-stop prior to entering the low power sleep state. 5 rtc the oscillator timing capacitor charge/d ischarge current control pin. a resistor is connected between this pin and gnd and determines the magnitude of the charge and discharge current. th e charge current is nominally 2x the current flowing into the resistor. the discharge current is nominally 8x the current flowin g into the resistor. the ratio of the charge to discharge cur rent is fixed and sets the maximum duty cycle at 80%. 6 ct the oscillator timing capacitor is connected between this pin and gnd. 7 iset controls the peak and average current limit thresh olds. a voltage up to 1.0v may be applied to iset. 8 verr the error voltage input to the pwm comparator and the comp ensation connection for the average current loop control. verr requires an external pull-up resistor to vref. a typical application conn ects the photo-transistor output of an opto-coupler be tween verr and gnd. 9 fb fb is the inverting input to the average current error amplifie r (iea). the amplifier is used as the error amplifier for the average current limit control loop. if the amplifier is not used, fb should be grounded. the am plifier is normally configured as an int egrator. 10 cs the current sense input to the ic. provides information to th e pwm, the peak overcurrent protection comparators, and the av erage current limit circuitry. the cs pin is shorted to gnd when th e pwm output pulse terminates. depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal logic and the turn off of the e xternal power switch. 11 iout output of the sample and hold buffer amplifier that captur es and averages the cs signal. with a nominal 4x multiplier and the ability to scale the signal externally with a resistor divider, the av erage current limit can be set independently of the peak current limit.
ISL6726 3 fn7654.0 january 31, 2011 12 slope a slope compensation capacitor is connected between slope and gnd. a current source of 100a charges the capacitor durin g the on time and discharges it during the off time. the amplitude of the signal is multiplied by a gain of 0.2 and summed with t he cs input. 13 outac the active clamp output for driving an external power swit ch. outac is capable of driving either a p- or n- channel clam p device and is configured by delay. 14 vdd vdd is the power connection for the ic. to optimize noise immunity, bypass vdd to gnd with a ceramic capacitor as close to the vdd and gnd pins as possible. vdd is monitored for undervoltage (u vlo). when vdd is below the uvlo threshold, the ic is disable d and the reference voltage, vref, is turned off. 15 outm the main pwm output for driving an external power switch. 16 gnd logic and power ground for this device. due to high peak cu rrents and high frequency operat ion, a low impedance layout is necessary. ground planes and shor t traces are highly recommended. 17 vref the 5.00v reference voltage output having a -2/+1.5% tolera nce over line, load and operatin g temperature. bypass to gnd with a 0.1f to 2.2f low esr capacitor. vref can source up to 10ma. 18 delay the delay pin configures outac for ei ther n-channel or p- channel drive compatib ility by setting the phase and the durati on when both the main and active clamp outputs are off. a resistor from de lay to vref sets an out-of-phase (non-overlap) relationship f or an n-channel clamp device with adjustable deadtime. a resistor fr om delay to gnd sets an in-phase (overlap) relationship for a p-channel clamp device with an adjustable symmet ric non-overlap duration between outm and outac. 19 mode the mode pin configures the ic for standard or synchronous rectification operation. if mode is connected to vref, standar d rectification operation is selected. soft-s top and the minimum duty cycle clamp are disabled. if mode is connected to gnd, synchronous rectification oper ation is enabled allowing soft-stop and the minimum duty cycle clamp to function. 20 ss connect the soft-start timing capacitor between this pin and gnd to control the duration of soft-start and soft-stop. the v alue of the ss capacitor determines the rate of increase and decrease of the duty cycle during start-up and soft-stop. soft-stop is enabled/disabled by mode. pin descriptions (continued) pin # symbol description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6726aaz ISL6726 aaz -40 to +105 20 ld qsop m20.15 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL6726 . for more information on msl, please see technical brief tb363 .
ISL6726 4 fn7654.0 january 31, 2011 internal architecture v ref 5.00 v 1% gnd vdd vref sync uv 1.00 v ct i dch on on outm outac cs verr oc detect ss internal ot shutdown 130 - 150 c i ch = 2 x i rtc v ff = 1.0 - 5.0 v i ch + - rtc i rtc i dch = 8 x i rtc v ff = 1.0 - 5.0 v + - delay + - dclim iset slope + - iout fb iset vref inhibit mode vref vdd sync bi-directional sync circuit sync out phase-shifted 180 o clk uvlo on oscillator clk ____ clk ct leading edge blanking pwm soft-start/ soft-stop average current limit ext. sync current amplifier vref output delay control and steering logic soft-start pwm out mode duty limit oc cs slope verror cs iout clk pwm out outclamp delay inhibit enable uvlobias uvlobias disable disable
ISL6726 5 fn7654.0 january 31, 2011 typical application using ISL6726 - active clamp forward with synchronous rectification vin+ vin- return t1 +vout c1 q1 c7 c2 c3 c13 u1 q2 cr1 r4 r22 t2 c12 c9 cr2 l1 r19 r20 r21 c11 c10 u2 u4 r16 r18 vr1 r17 r1 r2 c6 c8 c4 + r6 vcc (+10v) q3 q4 sync r3 r5 r7 r8 r9 r10 r11 r12 r13 r15 c5 t2 c14 r25 c15 cr3 q5 r23 r22 r24 on/off ct dclim verr vdd vref rtc delay iset cs mode ss enable uv slope gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 iout fb outm outac ISL6726 9 10 17 18 sync r14
ISL6726 6 fn7654.0 january 31, 2011 typical application using ISL6726 - active clamp forward with diode rectification vin+ vin- return t1 +vout c1 q1 c7 c2 c3 c13 u1 q2 cr1 r4 r22 t2 c12 c9 cr2 l1 r19 r20 r21 c11 c10 u2 u4 r16 r18 vr1 r17 r1 r2 c6 c8 c4 + r6 vcc (+10v) cr3 cr4 sync r3 r5 r7 r8 r9 r10 r11 r12 r13 r15 c5 ct dclim verr vdd vref rtc delay iset cs mode ss enable uv slope gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 iout fb outm outac ISL6726 9 10 17 18 sync on/off r14
ISL6726 7 fn7654.0 january 31, 2011 absolute maximum rating s thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +22.0v outm, outac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd signal pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 5v peak gate current, outm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3a peak gate current, outac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2a esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . 250v charged device model (tested per jesd-c101e) . . . . . . . . . . . . . . 1.5kv latch up (tested per jesd-78b; class2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 20 lead qsop (notes 4, 5) . . . . . . . . . . . . . 86 38 maximum junction temperature . . . . . . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range ISL6726axx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . . . . 9vdc to 16vdc caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 5. for jc , the ?case temp? location is taken at the package top center. 6. all voltages are to be measured with re spect to gnd, unless otherwise specified. electrical specifications recommended operating conditions unless otherwise no ted. refer to the block diagram on page 4 and the typical application schematics on pages 5 and 6. 8v < v d < 20v, r tc = 10.0k ? , c t = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. parameter test conditions min (note 7) typ max (note 7) units supply voltage supply voltage 12 20 v start-up current, i dd v dd < start threshold 50 125 400 a operating current, i dd c outm, outac = 0nf, v dd = 12v 10 11 ma c outm, outac = 0nf, v dd = 20v 12 13 c outm, outac = 1nf, v dd = 12v 18 20 ma uvlo start threshold 7.40 7.65 8.00 v uvlo stop threshold 6.00 6.23 7.00 v hysteresis 1.00 1.40 2.00 v voltage reference overall accuracy i vref = 0 to -10ma 4.900 5.00 5.075 v long term stability t a = +125c, 1000 hours 3 mv operational current (source) -10 ma current limit -25 -100 ma current sense current limit threshold, iset minimum 0.35 v current limit threshold, iset maximum 1.000 1.125 v cs to out delay 100 ns cs to pwm comparator offset v slope = 0v 90 100 110 mv cs discharge device, r ds(on) 15 31 ? cs input bias current -1 1 a iset input bias current -1 1 a leading edge blanking (leb) duration 75 100 130 ns
ISL6726 8 fn7654.0 january 31, 2011 iout buffer gain t a = +25c 3.90 4.00 4.12 v/v iout voh voh , (voh iload=0a - voh iload=-300a ), cs = 0.5v, iset = 1.00v 0.05 0.2 v iout vol i load = 100a, cs = 0v, iset = 1.00v 0.05 0.1 0.15 v slope compensation charge current slope = 2v -90 -100 -110 a slope compensation gain fraction of slope voltage added to cs 0.190 0.200 0.210 v/v slope discharge device, r ds(on) 50 ? slope range, linear response 02.5 v pulse width modulator minimum duty cycle mode = 5v, verr < 0.6v 0 ns mode = 0v, verr < 0.6v 270 300 350 ns maximum duty cycle 4.8 < verr < vref, uv = 4.2v, dclim > 4.0v 76 80 84 % rtc = 25.5k , ct = 220pf 80 % ss to pwm comparator input gain 0.23 0.25 0.27 v/v verr to pwm comparator input gain 0.28 0.30 0.32 v/v verr to pwm comparator input offset 0.60 0.80 1.00 v outm to outac delay timing delay gain overlap, t a = +25c 1.54 1.83 2.11 ns/k ? non-overlap, t a = +25c 1.54 1.79 2.11 ns/k ? delay range 50 500 ns delay disable, high 4.9 v delay disable, low 0.100 v oscillator frequency accuracy t a = +25c 326 338 349 khz frequency variation with vdd t a = +105c, |(f 20v - f 8v )/f 8v |, uv = 2.00v (note 7) 0.1 0.3 % t a = +25c, |(f 20v - f 8v )/f 8v |, uv = 2.00v 0.2 0.6 % t a = -40c, |(f 20v - f 8v )/f 8v |, uv = 2.00v (note 7) 0.6 8.0 % frequency variation with uv t a = +25c, |(f 4.25v - f 2.00v )/f 2.00v | vdd = 8v 0.1 1.5 % vdd = 20v 0.3 5.2 % temperature stability uv = 2.0v, vdd = 8v 0.5 1.5 % charge current gain rtc = 10.0k ? , 100k ? 1.88 2.0 2.12 a/a discharge current gain rtc = 10.0k ? , 100k ? 6.0 7.2 8.2 a/a ct valley voltage static operation 0.75 0.80 0.85 v ct peak voltage static operation uv = 2.00v 2.30 2.40 2.50 v uv = 4.00v 3.80 4.00 4.20 v electrical specifications recommended operating conditions unless otherwise no ted. refer to the block diagram on page 4 and the typical application schematics on pages 5 and 6. 8v < v d < 20v, r tc = 10.0k ? , c t = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter test conditions min (note 7) typ max (note 7) units
ISL6726 9 fn7654.0 january 31, 2011 rtc voltage r load = open uv = 2.00v 1.55 1.60 1.65 v uv = 4.00v 3.10 3.20 3.30 v soft-start iss charge current ss = 2v -45 -55 -65 a iss discharge current, absolute value mode = 0v, ss = 2v -45 -55 -65 a ss clamp voltage 4.5 4.6 4.7 v reset threshold voltage ss decreasing 0.15 0.20 0.25 v ss discharge current mode = 5v, ss = 2v 10.0 ma uv undervoltage input voltage low/inhibit threshold 0.97 1.00 1.03 v hysteresis, switched current amplitude 6.2 10 14 a input high clamp voltage 4.8 v input impedance 1 m ? maximum control voltage 4.20 vref v output outm, outac high level output voltage (voh) outm vdd - v outm or v outac 0.5 v outac i out = -100ma 1.0 v low level output voltage (vol) outm i out = 100ma 0.5 v outac 1.0 v rise time outm c gate = 1nf, v dd = 8v 15 30 ns outac 30 60 ns fall time outm c gate = 1nf, v dd = 8v 10 20 ns outac 20 40 ns uvlo output voltage clamp vdd = 5v outm, outac i load = 1ma 1.5 v dclim input bias current -1 1 a maximum control voltage 4.00 vref v mode high level input voltage (vih) 2 v low level input voltage (vil) 0.8 v pull-up resistance, internal 100 k ? electrical specifications recommended operating conditions unless otherwise no ted. refer to the block diagram on page 4 and the typical application schematics on pages 5 and 6. 8v < v d < 20v, r tc = 10.0k ? , c t = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter test conditions min (note 7) typ max (note 7) units
ISL6726 10 fn7654.0 january 31, 2011 enable high level input voltage (vih) 2 v low level input voltage (vil) 0.8 v pull-up resistance, internal 275 k ? error amplifier operating input range verr = fb, iset = 0v, 4v 04.00 v unity gain band-width product 8mhz fb bias current -1 1 a verr vol i load = 5ma, fb = vref, iset = 1v 0.40 v verr pull-up current source verr = fb = 0v, iset = 1v 100 a synchronization vil 0.8 v vih 2.0 v vol i load = 10 a 100 mv voh i load = -1.0ma 4.0 4.5 v source current voh > 2.0v -10 ma sink current vol < 2.5v 10 ma output duration 200 575 ns input duration, minimum 100 ns maximum frequency, input 2 mhz thermal protection thermal shutdown 145 c thermal shutdown clear 130 c hysteresis, internal protection 15 c note: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications recommended operating conditions unless otherwise no ted. refer to the block diagram on page 4 and the typical application schematics on pages 5 and 6. 8v < v d < 20v, r tc = 10.0k ? , c t = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter test conditions min (note 7) typ max (note 7) units
ISL6726 11 fn7654.0 january 31, 2011 typical performance curves figure 1. oscillator frequency vs ct and rtc f igure 2. oscillator frequency vs temperature figure 3. delay time vs resistance figure 4. delay time vs temperature (overlap) figure 5. delay time vs temperature (non -overlap) figure 6. vref vs temperature 0.1 1 10 10 100 1000 rtc = 10k ? ct (nf) frequency (khz) rtc = 25k ? rtc = 50k ? -40 -25 -10 5 20 35 50 65 80 95 110 0.990 0.995 1.000 1.005 1.010 temperature (c) normalized frequency 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 0 100 200 300 400 500 600 delay resistance (k ? ) delay time (ns) non-overlap overlap -40 -25 -10 5 20 35 50 65 80 95 110 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 temperature (c) normalized delay rdelay = 20k rdelay = 200k rdelay = 120k -40 -25 -10 5 20 35 50 65 80 95 110 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 temperature (c) normalized delay rdelay = 20k rdelay = 200k rdelay = 120k -40 -25 -10 5 20 35 50 65 80 95 110 0.990 0.995 1.000 1.005 1.010 temperature (c) normalized v ref
ISL6726 12 fn7654.0 january 31, 2011 functional description features the ISL6726 pwm is an excellen t choice for low cost high performance applications requiring d (duty cycle) and 1-d control signals. this includes ac tive clamp forward, asymmetric half-bridge, and synchronous rect ified (sr) standard forward and flyback topologies. among its many features are: ? high current fet drivers ? adjustable soft-start and soft-stop ?slope compensation ? programmable deadtime control ? overlapping and non-overlapping output configuration for both n-channel and p-channel clamp configurations ? peak and average overcurrent protection ? internal thermal protection ? minimum duty cycle clamp ? input voltage dependent maximum duty cycle clamp supply currents the total supply current, idd, will be dependent on the load applied to outputs outm and outac. total idd current is the sum of the quiescent current and the averag e output current. knowing the operating frequency (f sw ) and the output loading capacitance charge (q) per output, the average output current can be calculated from equation 1: oscillator the ISL6726 oscillator has a programmable frequency range to 2mhz, and can be set with one resistor and one capacitor. the use of two timing elements, rtc, and ct allow great flexibility and precision when setting the oscillator frequency. the switching period is the sum of the timing capacitor charge and discharge durations. the charge and discharge duration is determined by rtc and ct. where t c and t d are the charge and discharge times, respectively, t sw is the oscillator free running period, and f sw is the oscillator frequency. the actual times will be slightly longer than calculated due to inte rnal propagation delays of approximately 10ns/transition. this delay adds directly to the switching duration, but also causes overshoot of the timing capacitor peak and valley volt age thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. additionally, if very low charge and discharge currents are used, there will be increased error due to the input impedance of the ct pin. the timing component tolerance directly effects the oscillator accuracy. a npo/cog dielectric ceramic capacitor or better is suggested for ct. rtc should be 1% tolerance or better. figure 1 graphically portrays the oscillator frequency as function of the timing components. the minimum deadtime is fixed at 20% of the period allowing an 80% maximum duty cycle. this limits the maximum voltage stress on the power mosfets to 5x the input voltage. for applications that cannot tolerate this voltage stress, the maximum duty cycle can be reduced using the dclim feature. the peak voltage stress for an active clamp topology is approximately v in /(1-d). soft-start/soft-stop operation the ISL6726 features a soft-start using an external capacitor in conjunction with an internal current source. soft-start reduces stresses and surge currents during start-up. soft-stop reduces electrical stresses during shutdo wn when synchronous rectifiers (srs) are used and prevents polarity reversal of the converter output. soft-stop may be inhibited with mode for applications not using srs. the soft-start feature clamps the duty cycle for the duration of soft-start. the duty cycle is initially forced to zero and allowed to linearly increase until the cont rol loop takes control. at the beginning of a soft-start cycle, the ss capacitor is discharged. if enable is open and there is no uvlo fault on vdd, a current source charges the soft-start capa citor. taking into account the internal gains and offsets of verr and ss, soft-start limits the peak current amplitud e as long as it remains below verr. as the ss voltage increases, the peak current amplitude is allowed to increase. the output pulse width increases accordingly, until the ss voltage exceeds verr and the control loop takes over. the ss voltage will continue to increase until it reaches its clamp voltage of 4.6v even though soft-s tart is actually finished when the control loop takes over. the duty cycle increases from zero to its steady state operating point during the soft-start period. the soft-start waveform is shown in figure 7 for the non-overlap configuration, appropriate for th e active clamp forward with a n-channel clamp fet or the asymmetric half-bridge topology. for the active clamp topology usin g a p-channel clamp fet, the overlap configuration is required and the outac waveform shown in figure 7 would be inverted. the non-overlap configuration is shown for clarity. (eq. 1) i out 2qf sw ? ? = t c 0.5 rtc ? ct ? s (eq. 2) t d 0.125 rtc ? ct ? s (eq. 3) t sw t c t d + 1 f sw ---------- - == s (eq. 4) 1.2(v err -v offset ) 0.27v v ss =i ss *t/c ss 0.0v outm outac cs soft-start ends soft-start begins figure 7. soft-start function (i delay positive)
ISL6726 13 fn7654.0 january 31, 2011 the soft-stop function is en abled when mode=0. the ISL6726 enables a soft-stop when uv falls below 1v or when enable is pulled low (disable), causing a controlled discharge of the ss capacitor at the rate equal to and opposite of soft-start. soft-stop will not occur for a uvlo fault on vdd regardless of the mode setting. soft-stop continues until the ss pin voltage drops below ~0.25v, even if the fault condition is removed before the threshold is reached. using soft-stop forces an orderly shutdown of a converter that uses synchronous rectification (sr). it prevents the output voltage from going negative by co ntrolling the rate at which the output voltage is discharged thro ugh the output inductor. it also prevents the srs from being av alanched if sr operation is stopped when the inductor current is negative. if a self-driven sr method is used, the behavior during turn-off is improved as well. during soft-stop, the forward rectifier pulse width is slowly decreased to its minimum while the free-wheeling rectifier pulse width is slowly increased to its maximum. the active clamp capacitor voltage, v in /(1-d), approaches v in as the duty cycle approaches zero. the freewheeling rectifier gate voltage is v in d/n(1-d), where n is the transformer turns ratio np/ns, and decreases with decreasing duty cycle. at some point the voltage applied to the gate is insufficient to turn on the sr fet and negative inductor current is prevented. a hard-stop with self-driven srs re sults in oscillation of the srs because the output voltage can provide gate voltage through the output inductor and secondary winding. minimum duty cycle clamp in addition to soft-stop when mode=0, the minimum pulse width of outm is clamped to ~300ns independent of the pwm modulator. higher duty cycles are obviously allowed depending on the operating conditions, but shorte r duty cycles are not. in sr applications, this feature prevents excessive negative output inductor current if the output should experience a large and sudden reduction in load, such as occurs during a 100% to 0% load transient. a sudden load du mp can cause the control loop error voltage to drop sufficiently to command 0% duty cycle. this sets the forward rectifier to 0% duty cycle and the free-wheeling rectifier to 100% duty cycle. th is condition allows the inductor current to ramp to a large negati ve amplitude until the duty cycle again becomes non-zero. due to the normal deadtime allowed for proper switching of the srs, the forward rectifier will avalanche when the duty cycl e becomes non-zero. when the forward sr turns on, the inductor current will reflect to the primary and stress the components there as well. with the minimum duty cycle clamp feature, the forward rectifier turns on for ~300ns each cycle and prevents the large negative current in the output inductor. gate drive the ISL6726 has two outputs, outm and outac. outm is capable of sourcing 1a and sinking 1.5a peak current, and outac is capable of sourcing 0.5a and sinking 0.75a peak current. outac is configured using the delay input for either overlap or non-overlap phasing relative to outm. when configured for non-overlap phasing, outac operates at 1-d with deadtime, where d is the duty cycle of outm. this configuration is useful for the n-channel acti ve clamp and asymmetric half- bridge topologies. when configur ed for overlap phasing, outac has symmetric rising edge advance and falling edge delays relative to outm. this configurat ion is useful for the p-channel active clam p topology. two typical active clamp converte r configurations are shown in figures 9 and 10, with overlap or non-overlap delay time accurately set by a programmin g resistor. the rising edge overlap and the falling edge overlap time (or rising edge deadtime, and falling edge deadtime) are equal and independent of the operating frequency or duty cycle. to limit the peak current through the ic, an external resistor may be placed in series between an output and the gate of the mosfet. the resistor also dampens any oscillation caused by the resonant tank of the parasiti c inductance of the pwb traces and the fet gate input capacitance. the overlap/non-overlap delay between outac and outm prevents simultaneous conduction of the main and clam p switches in an active clamp converter, or the upper and lower switches in an asymmetric half- bridge converter. table 1 shows the combinations of the settings with the corresponding features fo r different topologies. 1.2(v err -v offset ) 0.27v v ss =5v-i ss *t/c ss 0.0v outm outac cs soft-stop begins soft-stop ends figure 8. soft-stop function (i delay positive) outac lm tx vdc +vout + vout = vin*d*ns/np vx vy outm outac outm d td = k1*rdelay td = k1*rdelay figure 9. output timing diagram for p-channel active clamp
ISL6726 14 fn7654.0 january 31, 2011 overlap phasing results when a resistor is connected between delay and gnd. non-overlap phasin g results when a resistor is connected between delay and vref. the resistor value determines the magnitude of the delay. the delay feature may be disabled by connecting delay directly to gnd or vref, depending on which configuration is desired, overlap or non-overlap. the non-overlap time in the overlap mode can be calculated using equation 5. the deadtime in non-overlapping mode can be calculated using equation 6. see figure 3 for typical delay gain curves. overcurrent operation the ISL6726 has two mechanisms for current limit. the peak current limit function provides cycle-by-cycle overcurrent protection. the protection threshold is set by a voltage applied to iset. if the peak current at cs exceeds iset, the outm pulse is terminated for the remainder of the switching cycle. peak current limit has some shortcomings that discourage its use as the only current limit mechanism. first, there is the slope compensation ramp that adds to the current feedback signal. its contribution to the cs signal vari es with duty cycle, and at high duty cycles it has a larger contribution than at lower duty cycles. as an overload condition causes the duty cycle to decrease, the portion of the current feedback contributed by the slope compensation decreases and the amount contributed by the current feedback increases. the result is that the maximum output current will increase as the output voltage decreases. another phenomenon occurs when the duty cycle is reduced to the minimum pulse width the ic controller is capable of producing. if the output voltage is reduced below the value corresponding to this duty cycle, current tail-out occurs. there is a certain amount of energy deli vered to the output on each switching cycle that must corresp ond to voltage and current at the load. if the voltage is very low due to a shorted output, large currents can result. some controllers solve the problem by allowing the converter to cycle on and off (hic-cup operation) to lower the average short circuit current. this works accept ably for some applications, but not when redundancy or parallel operation is required. such behavior can prevent a successful fault recovery when the short is removed. the paralleled or redundant units will not hic-cup in unison, and each will experience an overload condition each time a restart is attempted. an ideal current limiting meth od requires a constant value regardless of the output voltag e, the so-called ?brick-wall? current limit. the output current remains constant from current limit inception to a short circuit. the ISL6726 provides this behavior with the average current limit function. the average current limit feature uses a patented circuit that samples the current feedback signal and creates a signal proportional to the average value of the output inductor current. the signal, analogous to the voltage feedback signal of voltage control loop, becomes the feedback signal for the current error amplifier and produces a curre nt error signal. the voltage feedback and current feedback share a common control node table 1. mode and delay settings for typical topologies topology mode delay phasing soft-stop minimum d clamp n-fet active clamp with diode rectification high r to vref non-overlap disabled disabled p-fet active clamp with diode rectification high r to gnd overlap disabled disabled n-fet active clamp with sr rectification low r to vref non-overlap enabled enabled p-fet active clamp with sr rectification low r to gnd overlap enabled enabled standard forward with diode rectification high = 0v, = vref overlap, non-overlap disabled disabled asymmetric half-bridge low r to vref non-overlap enabled enabled lm tx vdc +vout + vout = vin*d*ns/np vx vy outm il is1 is2 is imag outac td = k2*rdelay td = k2*rdelay outm figure 10. output timing diagram for n-channel active clamp t delay 1.83 ns k ------- - r delay k () 13ns + ? = (eq. 5) t delay 1.79 ns k ------- - r delay k () 9ns + ? = (eq. 6)
ISL6726 15 fn7654.0 january 31, 2011 (verr) used by the pulse width modulator. whichever error signal, voltage or current, that commands the lower duty cycle is in control. if the average current is lower than the average current limit threshold, the current error amplifier has no impact on verr and the voltage loop is in control. if the average current limit threshold is exceeded, however, the current error amplifier will lower verr to regulate the output current. the voltage loop loses control as it must increase the duty cycle to maintain the output voltage in regulation. after a 100ns leading edge blanking (leb) delay, the current sense signal is sampled for the duration of the on time, the average current is determined, and the result is amplified by 4x and output to the iout pin at the termination of the outm pulse. due to the sampling algorithm used, if an rc filter is placed on the cs input, its time constant should not exceed ~30ns or error may be introduced on iout. the average current signal on iout produces an accurate representation of the output current provided the converter operates in continuous conduction mode (ccm). once the inductor current becomes discon tinuous (dcm operation), iout represents one half of the peak inductor current rather than the average current. this occurs because the sample and hold circuitry is active only during the on time of the switching cycle and cannot determine when the inductor current becomes discontinuous. it is unable to detect when the inductor current reaches zero during the off time. this behavior does not affect the average current limit function, but does have an impact if iout is used for current monitoring functions. iout may be used with the availa ble error amplifier (ea) of the ISL6726 as shown in figure 13. the error amplifier is typically configured as an integrator. as shown in figure 13, iout is attenuated by resistors r 1 and r 2 so that the average current limit threshold can be set inde pendently of the peak current limit threshold. the integrator bandwidth is determined by r and c. the current error amplifier is similar to the voltage ea found in most pwm controllers, except it cannot source current. verr requires an external pull-up resistor. the iea is configured as an integrating (type i) amplifier using iset as the reference. the voltag e applied at fb is integrated against the iset reference. the re sulting signal, verr, is applied to the pwm comparator where it is compared to the current signal cs. if fb is less than iset, the iea will be open loop (can?t source current), verr will be at a level determined by the voltage loop, and the duty cycle is unaffected. as the output load increases, iout will increase, and the voltage applied to fb will increase until it reaches iset. at this point the iea will control verr as required to maintain the output current at the level that corresponds to the iset reference. when the output current again drops below the average cu rrent limit threshold, the iea returns to an open loop condition, and the duty cycle is again controlled by the voltage loop. the average current control loop behaves much the same as the voltage control loop found in typical power supplies except it regulates current rather than voltage. figure 11. cs input vs iout channel ? 1: ? outm ? ????????????? channel ? 2: ? iout ? ?????????????? channel ? 4: ? cs figure 12. dynamic behavior of cs and iout channel ? 1: ? outm ? ????????????? channel ? 2: ? iout ? ?????????????? channel ? 4: ? cs figure 13. average current configuration + - r r1 r2 c verr iset cs 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 iout fb ISL6726 9 10 17 18 vref s&h 4x r pull-up
ISL6726 16 fn7654.0 january 31, 2011 the average current loop bandwidth is normally set much lower than the switching frequency, typically less than 5khz and maybe as slow as a few hundred hertz, depending on the application requirements. this is especially useful if the application experiences large surges. the average current loop can be set to the steady state overcurrent threshold and have a time response that is longer than the required transient. under some conditions it will be necessary to clamp the fb pin with a schottky diode to signal gr ound. if the voltage loop causes a fast decreasing transient on verr, the feedback capacitor between verr and fb can cause a negative voltage on fb and violate the absolute maximum rating. duty cycle clamp it is very important to contro l the maximum duty cycle of an active clamp reset forward converter. the clamp capacitor and drain-source voltage of the main switch is related to the duty cycle d by equation 7. if the duty cycle is not clamped, the fet drain-source voltage can become quite high and overstress the fet. without the input voltage depend ent maximum duty cycle clamp it is possible to have both high input voltage and high duty cycle during input voltage or load transients. the duty cycle clamp reduces the maximum duty cycle as the input voltage increases. whereas the maximum duty cycle at minimum input voltage is large, it is not necessary, nor is it advantageous, to have the same maximum duty cycle at maximum input voltage. the duty cycle clamp allows the designer to provide a constant margin of duty cycle headroom above the steady state operating point to allow for adequate dynamic response without allowing so much headroom that it can result in excessive voltage stress on the fet. during transients the situation is particularly bad, not only because of the voltage stress on the power fets, but also because the clamp capacitor voltage is not at the steady state voltage required to properly re set the transformer. the active clamp forward topology is also know as the optimum reset topology because the steady state clamp capacitor voltage is exactly the value required to rese t the core during the off time. however, it can take many switching cycles before the clamp capacitor voltage reaches a new steady state value after a change in operating point. if th e clamp capacitor voltage is lower than required, the transformer co re is not reset completely and can lead to transformer saturation after a few switching cycles. this condition occurs when the input voltage is rapidly decreased, or when the output load is rapidly increased. both of these conditions result in a rapidl y increasing duty cycle. if the duty cycle can increase more quickly than the clamp capacitor voltage can respond, the core will not be properly reset. one or the other of these transients can be mitigated by the sizing of the clamp capacitor value. smaller values favor input voltage transient behavior whereas larger values favor load transient behavior. most designs favor load transient behavior. in either case, the maximum duty cycle clamp prevents large duty cycle increases and limits tr ansformer flux dens ity and fet voltage stress. the main output pwm is controll ed by the current and voltage feedback signals. when the feedback loop demands maximum duty cycle, the duty cycle is limited by the lesser of the input voltage-dependent duty cycle limiter or the maximum duty cycle limit of the controller, which is 80% by design. the input voltage dependent duty cycle limit is inversely proportional to the input voltag e, as shown in figure 15. the voltage applied to uv determines the amplitude of the ct sawtooth waveform, where ct peak = 0.8 + 0.8 * uv. since the uv turn-on threshold is 1.00v, the minimum amplitude of ct is 1.60v. at uv = 4.00v, the amplitude of ct is 4.00v. the maximum duty cycle clamp is determined by the voltage applied to dclim and the amplitude of ct. if dclim is set to 1.60v or greater, the maximum duty cycle is 80%. the maximum duty cycle as a function of uv and dclim is: for most applications the maximum duty cycle will be set for the minimum operating input voltage, and for which uv is set to 1.00v. consequently, the actual duty cycle of the main output, outm, is the minimum of the current mode pwm comparator, the maximum 80% duty cycle clamp of the controller, or the input voltage dependent duty cycle clamp. 1v uv = k*vin 1.2v duty cycle clamped by uv 5v duty cycle maximum duty cycle clamp minimum duty cycle clamp mode = gnd figure 14. duty cycle clamp vds vin 1d ? () ----------------- - = (eq. 7) d max dclim 0.8 ? uv -------------------------------- - dclim 0.8 uv 0.8 + ? , = 0.8 dclim 0.8 uv 0.8 + ? > , = (eq. 8)
ISL6726 17 fn7654.0 january 31, 2011 synchronization ISL6726 provides a single i/o pi n synchronization function that allows synchronization to an extern al clock or to self-synchronize to another unit at ~180 degree s out-of-phase for interleaved applications. when using an extern al clock, the clock pulse width must be a minimum of 100ns. the clock frequency must be higher than the free running frequency of the oscillator. multiple units may be synchronized together simply by connecting the sync pins together as shown in figure 16. in this configuration all of the devices wi ll synchronize out-of-phase with the master. the master is usually the unit with the fastest free- running oscillator, but may not be due to intentional hysteresis within the arbitration circuitry. synchronization occurs on the leading edge of the sync signal. however, no unit will accept a sync pulse while its oscillator ramp voltage is less than 3/8 of the timing capacitor voltage peak voltage. this prevents short cycling of the period. if the sync pins of multiple devices are connected together, the first sync signal that asserts will reset the oscillator ramp of all other devices. further arbitration may occur if there is a higher frequency unit present. all slave controllers will operate out-of- phase with the master. multiple devices may be synchronized in this fashion, but the number wi ll depend on the distance and capacitance of the sync signal path. care should be taken to ensure the ground potential difference between devices is minimized. in most cases an external clock is used to synchronize more than two units. 0.8v uv v pk =0.8uv+0.8 1.6uv/(c tc *r tc ) t 1 =1/2c tc *r tc t 2 =1/8c tc *r tc dclim t 1 t 2 t dc = v dc /v pk *t 1 intrinsic maximum d maximum d set by dclim cs figure 15. maximum duty cycle clamp using dclim figure 16. synchronizing two units ct gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 outm ISL6726 9 10 17 18 sync ct gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 outm ISL6726 9 10 17 18 sync outm1 outm2 outm1 outm2 ct1 ct2 ct1 ct2
ISL6726 18 fn7654.0 january 31, 2011 configuring uv the uv input is used for input source undervoltage lockout. if the uv node voltage falls below 1.00v, a uv shutdown fault occurs. this may be caused by low source voltage or by intentional grounding of the pin to disable the outputs. there is a nominal 10a switched current source used to create hysteresis. the current source is active only during an uv/inhibit fault; otherwise, it is inactive and does not affect the uv threshold voltage. the magnitude of the hysteresis is a function of the external resistor divider impedance. if the resistor divider impedance results in too little hysteresis, a series resistor between the uv pin and the divider may be used to increase the hysteresis. a soft-start cycle begins when the uv/inhibit faul t clears. the voltage hysteresis created by the switched curr ent source and the external impedance is generally small due to the large resistor divider ratio required to scale the input voltag e down to the uv threshold level. referring to figure 17, as v in decreases to a uv condition, the threshold level is: the hysteresis voltage, v, is: setting r3 equal to zero result s in the minimum hysteresis, and yields: as v in increases from a uv condition, the threshold level is: although the current hysteresis prov ides great flexibility in setting the magnitude of the hysteresis voltage, it is susceptible to noise on the signal. if the hysteresis was implemented as a fixed voltage instead, the signal could be filtered with a small capacitor placed between the uv pin and signal ground. this technique does not work well when the hysteresis is a current source because a current source takes time to charge the filter capacitor. there is no instantaneous change in the threshold level thereby rendering the current hysteresis ineffective. to remedy the situation the filter capacitor must be separated from the uv pin by a resistor. referring to figure 17, the filter capacitor must be placed in parallel with r2, and the capacitor and r3 must be physically close to the uv pin. uv may also be used as an inhibit signal by externally pulling it below the 1v threshold. however, caution must be exercised as the maximum duty cycle limit controlled by dclim will be defeated. the peak amplitude of ct will be reduced to ~1.6v when uv decreases below the 1v turn-off threshold, and the maximum duty cycle allowed will increase to 80%. slope compensation for applications where the maximu m duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. the amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. for applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability, referred to as sub-harmonic oscillation. slope co mpensation is a technique in which the current feedback signal is modified by adding slope, that is, adding a linearly increasi ng voltage as a function of time. the minimum amount of slope compensation required corresponds to 1/2 the inductor downslope, as it would appear referred to the cs input. see figure 18. more may be added, but increasing the slope compensation arbitrarily results in a control loop that transitions into voltage mode as the slope compensation begins to dominate the current feedback signal. the minimum amount of capacitance to place at the slope pin is: where t on is the maximum on time in seconds, and v slope is the amount of voltage to be added as slope compensation to the current feedback signal at the cs pin. in general, the amount of slope compensation added is 2 to 3 times the minimum required. it should be noted that the power transformer magnetizing inductance contributes to slop e compensation and should be considered when determining the amount of slope compensation required. example: assume the inductor current signal presented at the cs pin decreases 125mv during the off period, and: switching frequency, f sw = 250khz duty cycle, d = 60% t on = d/f sw = 0.6/250e3 = 2.4s t off = (1 - d)/fsw = 1.6s figure 17. uv hysteresis v in r1 r2 r3 1.00v 10a on + - v in down () r1 r2 + r2 --------------------- - = v (eq. 9) v10 5 ? r1 r3 r1 r2 + r2 --------------------- - ?? ?? ? + ?? ? = v (eq. 10) v10 5 ? r1 ? = v (eq. 11) v in up () v in down () v + = v (eq. 12) c slope 18 t on v slope ------------------- - ? = f (eq. 13) isense signal (v) time downslope current sense signal figure 18. downslope
ISL6726 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7654.0 january 31, 2011 for additional products, see www.intersil.com/product_tree determine the downslope: downslope = 0.125v/1.6s = 78mv/s. now determine the amount of voltage that must be added to the current sense signal by the end of the on time. therefore, an appropriate slope compensation capacitance for this example would be 1/2 to 1/3 the calculat ed value, or between 150pf and 220pf. using mode the mode pin configures the ic for standard or synchronous rectification compatibility. if mode is connected to vref, standard rectification compatibility is se lected. soft-stop and the minimum duty cycle clamp are disabled. if mode is connected to gnd, synchronous rectification compatib ility is selected, and soft-stop and the minimum duty cycle clamp are enabled. thermal protection an internal temperature sensor protects the device should the junction temperature exceed +145c. there is approximately +15c of hysteresis. ground plane requirements careful layout is essential for sati sfactory operation of the device. a good ground plane must be employed. use a ground layer if possible. the power ground should be connected to the control ground at one point. vdd should be bypassed directly to gnd with good high frequency capacitance, such as a ceramic capacitor. a small ceramic capacitor is also recommended for dclim. the outm, and outac of ISL6726 are very fast signals, and should have very short direct paths to the power mosfets in order to minimize inductance in the pc board traces. the return path should be as short as possible. the components at the pins of ss, dclim, uv, delay, ct, and rtc should be as physically close as possible to the ic. proximity to high di/dt loops and high dv/dt nodes should be avoided. the cs signal requires proper filtering and the pwb layout is critical for normal operation of the current related functions. a rc filter may be required. the time constant should be no greater than 25ns to prevent incorrect average current information. if a current sense transformer is used, both leads of the secondary winding should be routed to the cs filter components and to the ic pins. the transformer return should be connected via a dedicated pc board trace to the gnd pin rather than through the ground plane. if a current sense resistor in seri es with the switching fet source is used, a low inductance resistor is recommended. the low level signals must avoid the high current path. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL6726 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear v slope 1 2 --- 0.078 2.4 ? ? 94mv == (eq. 14) c slope min () 18 6 ? 10 2.4 6 ? 10 0.094 ----------------------- - ? 470pf = (eq. 15) revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change january 31, 2011 fn7654.0 initial release.
ISL6726 20 fn7654.0 january 31, 2011 package outline drawing m20.15 20 lead quarter size outline plastic package (qsop) rev 2, 1/11 detail "x" side view typical recommended land pattern top view 0.010 (0.25) 0.007 (0.18) 8 0.050 (1.27) 0.016 (0.41) 20 123 index area (0.635 bsc) 0.025 1 2 0.025 (0.64) x 18 0.220(5.59) seating plane 0.015 (0.38) x 20 0.060 (1.52) x 20 3 20 3 4 5 0.244 (6.19) 0.228 (5.80) 0.157 (3.98) 0.150 (3.81) 0.344 (8.74) 0.337 (8.56) 0.069 (1.75) 0.053 (1.35) 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0 0.0196 (0.49) 0.0099 (0.26) 0.061 max (1.54 mil) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing conform to amse y14.5m-1994. 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. length of terminal for soldering to a substrate. 7. terminal numbers are shown for reference only. 8. dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of dimension at maximum material condition. 9. controlling dimens ion: inches. converted millimeter di mensions are not necessarily exact. 6 0.25 0.010 gauge plane 8

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